1. Field of the Invention
The present invention is related to an analysis system, or apparatus, and more specifically it relates to a system that analyzes the delay time in logic equipment.
In recent years, advancements in VLSI technology have enabled the manufacture of sophisticated logic equipment with high performance. However, in the development of such equipment, it is necessary to verify the speed performance of the equipment before manufacturing the equipment. Delay time analysis systems are used as tools to verify the performance of logic equipment at the design stage. However, with the appearance of complex, large-scale systems, huge amounts of calculations are required for analysis of delay times, resulting in a great increase in the amount of time required for analysis.
2. Description of the Related Art
In the past, as a means of checking the target performance of a piece of logic equipment, the maximum and minimum accumulated delay times between each flip-flop circuit of the equipment using the target cycle time, adding to these values the clock skew (the time skew between the clock signal at the sending flip-flop circuit and the clock signal at the receiving flip-flop circuit), a verification being performed for over-delay and racing. The over-delay check is a check of whether or not the minimum accumulated delay time between flip-flop circuits, even taking into consideration the clock skew, falls within the clock cycle of the equipment. The racing check is a check of whether or not the minimum accumulated delay time between flip-flop circuits, even taking into consideration the clock skew, is within the width of a clock pulse.
The following three previously known methods are used in calculating the accumulated delay time between flip-flop circuits and the clock skew. The all-pin event method is the method of performing a calculation of the accumulated delay time from a specified clock input pin, and further calculating the accumulated signal delay time required from the clock pins that each clock reaches and from the primary input pins. Should there be a gate circuit at which two signals merge together at a flip-flop circuit input pin, in the calculation of that delay time only the maximum (over-delay) and minimum (racing) accumulated delay times required to reach the above-noted input pin are propagated onward, the accumulated delay time of other paths not being propagated onward from this point.
The separate-clock even method is a method that considers the differences in clock systems, wherein a calculation of the accumulated delay time for each specified clock is performed separately. Therefore, even at the above-noted merging-point gate, if the specified clock for each path differs, the calculation will be performed corresponding to each path. However, in this case as well in the case in which each path input to the above-noted merging-point gate circuit uses the specified clock, only the path having the maximum or the minimum delay value is calculated, as in the all-pin event method described above.
The all-path trace method is the method in which the accumulated delay time for all paths to be calculated is calculated. Therefore, all the paths up to the desired flip-flop circuit are calculated.
However, each of the above-described methods presents the following problems.
In the above-described all-pin event method, because this is a method which uses either the minimum or the maximum delay value to represent the delay value in the case in which paths reconverge, in the case in which paths reconverge from flip-flop circuits which are driven by different clocks, the maximum or minimum delay value is determined without being able to consider the correct clock skew. For this reason, the problem of not being able to calculate the accumulated delay time accurately occurs.
In the above-described separate-clock even method, because delay values are calculated for each flip-flop circuit driven by the same clock, while the clock skew can be calculated accurately, even in the case of the same clock, because it is only possible to calculate the maximum or minimum accumulated delay time to reach the destination flip-flop circuit, it is not possible to determine the accumulated delay time of a bad path in relation to a different clock at the next path. This is a problem that is common to the above-described all-pin event method as well.
Further, in the above-described all-path trace method, because the worst path is determined by calculating the delay times for all the existing paths, the problem of requiring a huge amount of calculations and computer time exists. Therefore, in performing verifications on an actual piece of equipment, it is not possible to calculate all paths in a limited amount of time.
Two problems are held in common by the above-described methods. These are a first problem that the dispersion calculation by mean square method cannot be properly made due to the fact that it is not possible to recognize whether or not paths having the maximum or minimum accumulated delay time pass through one and the same LSI device, and a second problem of the difficulty in recognizing branch points in the clock system paths, making clock skew calculation impossible. The mean square method of calculating the dispersion is a statistical processing method of calculating an accumulated delay time that is the closest possible to an actual piece of equipment, this method being applied because of the variations in delay times introduced in the manufacturing process for LSI and other devices.